Currently, the semiconductor industry is at a rapidly developing stage, the requirement on the performances of various electronic devices becomes higher and higher, which inevitablely involves semiconductor memories widely used in various electronic products. Also, with the occurrence of large number of mobile electronic products (such as laptop PC, MP3, MP4, digital camera, etc.), the demand for nonvolatile semiconductor memory with high performance becomes more urgent.
In the whole development history of the nonvolatile semiconductor memories, flash memory is playing an important role. Since the 1980's when such memory emerged, the flash memory has always been a memory device widely used in the industry due to its excellent characteristics. This memory changes the threshold voltage of the whole device by storing or erasing electrons in a special structure of the device so as to accomplish the distinguishing between the two states of “0” and “1” and achieve the storage function. As for the said special structure for storing electrons, during the development of flash memory, there have been two forms emerged successively:
1. Floating Gate Flash Memory
With respect to the flash memory with such structure, the storage of electrons is achieved by using a polysilicon floating gate. Over a bulk silicon substrate 101, in addition to a source 102 and a drain 103, a tunneling oxide layer 104, a polysilicon floating gate 105, a block oxide layer 106 and a control gate 107 are sequentially arranged over a channel, as particularly shown in FIG. 1. It is to be indicated that the electrons of such structure are distributed continuously on the floating gate.
2. Discrete Trap Flash Memory
Compared with the floating gate flash memory, the structure for storing electrons of a discrete trap flash memory is a silicon nitride trap layer rather than a polysilicon floating gate, while the remaining structure of the discrete trap flash memory is substantially the same as that of the floating gate flash memory. The electrons stored in the silicon nitride layer are localized and are not continuous. Therefore, if a leakage path occurs due to the damage of the tunneling oxide layer, only the electrons in the path region are leaked through the leakage path, while the electrons stored in other parts are not reduced, so that the retaining characteristic of the whole device is improved.
During the later development, although a lot of intensive improvement works have been made on the basis of the above mentioned structures to meet various new requirements on storage, lots of improvements of the above two flash memory structures are not going well due to the limitation of their basic physical mechanisms. Especially, in the case where the whole semiconductor industry follows the Moor Law and the feature size is gradually scaled-down, the flash memory is facing with more serious challenges including, among others, inhibiting the punch-through effect in a short channel, increasing the programming efficiency and reducing the power consumption, etc.
On the other hand, a tunneling field effect transistor (referred as TFET) is a transistor based on the quantum tunneling effect. The structural difference between the tunneling field effect transistor and the conventional MOS transistor is that, in the tunneling field effect transistor, the source and the drain are of two different doping types and both an N type slightly doped silicon (N− type silicon) and a P type slightly doped silicon (P− type silicon) may be used as a substrate. FIG. 2 is a schematic diagram illustrating the structure of a TFET using an N− type silicon as a substrate 201, wherein an N+ terminal 202 and a P+ terminal 203 are on the two ends of the silicon plane respectively, and a gate oxide layer 204 and a polysilicon gate 205 are sequentially disposed over a channel. In the case where no external voltage is applied to each terminal, the energy band along the channel direction is shown in FIG. 3(a), in this case the whole transistor is in the off status. In the case where sufficient negative bias and positive bias are applied to the P+ terminal 203 and the N+ terminal 202, respectively and an appropriate positive bias is applied to the polysilicon gate 205, the energy band along the channel direction is shown in FIG. 3(b). If the biases applied are sufficient to bend the energy band of the interface between the P+ terminal 203 and the channel so that the band to band tunneling occurs, the electrons will tunnel to the conduction band of the channel region from valence band of the P+ terminal 203 so as to drift to the N+ terminal 202 under the action of the electric field along the channel direction. In this case, such transistor is used as an N type TFET, wherein the N+ terminal 202 is used as a drain while the P+ terminal 203 is used as a source. In the case where sufficient negative bias and positive bias are applied to the P+ terminal 203 and an N+ terminal 202, respectively, and an appropriate negative bias is applied to the polysilicon gate 205, the energy band along the channel direction is shown in FIG. 3(c). If the biases applied are sufficient to bend the energy band of the interface between the N+ terminal 202 and the channel so that the band to band tunneling occurs, the electrons will tunnel to the N+ terminal 202 from the valence band of the channel region, while the remaining holes will sweep to the P+ 203 rapidly under the action of a strong electric field. In this case, such transistor is used as a P type TFET, wherein the P+ terminal 203 is used as a drain while the N+ terminal 202 is used as a source.